It also states that the external clock input can track a signal ( normally below 50 Hz) up to 2kHz (i.e from a vco) and multiply it up to 16 kHz. This is an audio circuit and the specifications for the circuit state that the audio inputs and outputs ( rise and fall time = < 1us) can range from 0-24 kHz and that the sampling rate is at 48 kHz. The max clock frequency that the SDRAM can handle is 163 MHz. I read that any signal(s) above 50 MHz constitute a high-speed design, requiring special routing rules. I am trying to create a PCB (digital audio delay unit) from a schematic which includes a SDRAM, this is due to the fact that the circuit is supposed to be controlled from an external clock source and because the SDRAM is supposed to store audio data/signals (sampling). I am a chemistry student and I am beginning to realize that I have fallen into a EE rabbit hole.
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